1. Field of the Invention
The present invention relates to a manufacturing method for a variable resistive element having two electrodes and a variable resistor where the above described variable resistor is in such a region as to be sandwiched between the two electrodes, and the electrical resistance changes when a voltage pulse is applied between the two electrodes.
2. Description of the Related Art
In recent years, various device structures, such as FeRAM's (ferroelectric RAM's), MRAM's (magnetic RAM's) and PRAM's (phase change RAM's) have been proposed as next generation nonvolatile random access memories (NVRAM's), which make fast operation possible and substitute for flash memories, and severe competition in development has led to improvement in the performance, increase in the reliability, reduction in cost and improvement in the integration in the manufacturing process. These memory devices presently have both advantages and shortcomings, and we are far away from being able to implement an ideal “universal memory” having the respective advantages of SRAM's, DRAM's and flash memories.
Using existing technology, resistive nonvolatile memories RRAM (resistive random access memories) having a variable resistive element of which the electrical resistance reversibly changes when a voltage pulse is applied have been proposed. FIG. 26 shows the configuration of such a memory.
As shown in FIG. 26, conventional variable resistive elements have a structure where a lower electrode 103, a variable resistor 102 and an upper electrode 101 are layered in this order, and have such properties that the resistance value can reversibly change when a voltage pulse is applied between the upper electrode 101 and the lower electrode 103. The configuration allows a novel nonvolatile semiconductor memory device to be implemented by reading out the resistance value which changes during the reversible resistance changing operation (hereinafter referred to as “switching operation”).
This nonvolatile semiconductor memory device can be provided by forming a memory cell array where a number of memory cells having a variable resistive element are respectively aligned in rows and columns in a matrix, and providing a peripheral circuit for controlling data programming, erasing and reading operations in each memory cell in the memory cell array. In addition, there may be different types of memory cells for this device, depending on the composition, for example memory cells where each memory cell is formed of one selection transistor T and one variable resistance element R (referred to as “1T/1R type”) and memory cells where each memory cell is formed of one variable resistive element R (referred to as “1R type”). From among these, an example of the configuration of 1T/1R type memory cells is shown in FIG. 27.
FIG. 27 is an equivalent circuit diagram showing an example of the configuration of a memory cell array made up of 1T/1R type memory cells. The gate of the selection transistor T in each memory cell is connected to a word line (WL1 to WLn), while the source of the selective transistor T in each memory is connected to a source line (SL1 to SLn) (n is a natural number). In addition one electrode of the variable resistive element R in each memory cell is connected to the drain of the selection transistor T and the other electrode of the variable resistive element R is connected to a bit line (BL1 to BLm) (m is a natural number). In addition, the respective word lines WL1 to WLn are connected to a word line decoder 106, the respective source lines SL1 to SLn are connected to a source line decoder 107, and the respective bit lines BL1 to BLm are connected to a bit line decoder 105. Thus, certain bit lines, word lines and source lines are selected for programming, erasing or reading operations in certain memory cells within the memory cell array 104 in response to an address input (not shown) in the configuration.
FIG. 28 is a cross sectional schematic diagram showing one of the memory cells that form the memory cell array 104 in FIG. 27. In the present configuration, each memory cell is formed of a selection transistor T and a variable resistive element R. The selection transistor T is formed of a gate insulating film 113, a gate electrode 114, a drain diffusion layer area 115 and a source diffusion layer area 116 on the upper surface of a semiconductor substrate 111 where an element isolation region 112 is formed. In addition, the variable resistive element R is formed of a lower electrode 118, a variable resistor 119 and an upper electrode 120.
In addition, the gate electrodes 114 of the transistors T form word lines, and the source line wirings 124 are electrically connected to the source diffusion layer areas 116 of the transistors T via contact plugs 122. In addition, the bit line wirings 123 are electrically connected to the upper electrodes 120 of the variable resistive elements R via contact plugs 121, while the lower electrodes 118 of the variable resistive elements R are electrically connected to the drain diffusion layer areas 115 of the transistors T via contact plugs 117.
In this configuration, where the selection transistors T and the variable resistive elements R are aligned in series, the change in potential of the word lines allows the transistors of the selected memory cells to be in an on state, and furthermore, the change in potential of the bit lines allows only the variable resistive elements R of the selected memory cells to be selectively programmed or erased.
FIG. 29 is an equivalent circuit diagram showing an example of the configuration of a 1R type memory cell. Each memory cell is formed of only a variable resistive element R, so that one electrode of the variable resistive element R is connected to a word line (WL1 to WLn) and the other electrode is connected to a bit line (BL1 to BLm). In addition, the respective word lines WL1 to WLn are connected to a word line decoder 133 and the respective bit lines BL1 to BLm are connected to a bit line decoder 132. In addition, certain bit lines and word lines for programming, erasing or reading operations in certain memory cells within the memory cell array 131 are selected in response to an address input (not shown) in the configuration.
FIG. 30 is a schematic perspective diagram showing an example of the structure of a memory cell that forms the memory cell array 131 in FIG. 29. As shown in FIG. 30, an upper electrode wiring 143 and a lower electrode wiring 141 cross each other in the alignment, and one of these forms a bit line and the other forms a word line. In addition, variable resistor 142 is provided where the two electrodes intersect (usually referred to as “cross point”) in the structure. Though in the example in FIG. 30, the upper electrode 143 and the variable resistor 142 are processed so as to have the same form for the sake of convenience, the region which electrically contributes to the switching operation of the variable resistor 142 is the cross point where the upper electrode 143 and the lower electrode 141 cross.
Here, the variable resistor material used for the above described variable resistor 119 in FIG. 28 and the variable resistor 142 in FIG. 30 is disclosed by Shangquing Liu and Alex Ignatiev of Houston University in the US, in the specification of U.S. Pat. No. 6,204,139, and by Liu, S. Q. et al. in “Electric-pulse-induced reversible resistance change effect in magnetoresistive films,” Applied Physics Letter, Vol. 76, pp. 2749-2751, in 2000, which describe a method for reversibly changing the electrical resistance by applying a voltage pulse to a perovskite material which is known to have colossal magnet resistance effects. This method is state-of-the-art in that use of a perovskite material which is known to have colossal magnet resistance effects causes change of several digits in the resistance at room temperature without application of a magnetic field. Here, the element structure described in the specification of U.S. Pat. No. 6,204,139 uses a crystal praseodymium calcium manganese oxide Pr1-xCaxMnO3(PCMO) film, which is a perovskite-type oxide, as the material for the variable resistor.
As for other variable resistor materials, it is known from H. Pagnia et al., “Bistable Switching in Electroformed Metal-Insulator-Metal Devices,” Phys. Stat. Sol. (a), vol. 108, pp. 11-65, in 1988, and Japanese Translation of International Unexamined Patent Publication No. 2002-537627 and the like that oxides of transition metal elements, such as titanium oxide (TiO2) films, nickel oxide (NiO) films, zinc oxide (ZnO) films and niobium oxide (Nb2O5) films exhibit reversible change in the resistance. From among these, switching operation using NiO is reported in detail in Baek I. G. et al., “Highly Scalable Non-volatile Resistive Memory Using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses,” IEDM 04, pp. 587-590, in 2004.
According to the above described prior art, variable resistive elements R are formed by layering a lower electrode, a variable resistor and an upper electrode on a substrate in this order. Therefore, in order to gain variable resistive elements having a stable switching operation with excellent reproducibility, it is essential for the contact resistance between the lower electrode and the variable resistor and the contact resistance between the variable resistor and the upper electrode to be consistent among memory cells within the same wafer, as well as among the wafers.
In accordance with conventional methods, however, the surface of the electrodes and the variable resistor is exposed to gases and chemicals used in the process, therefore, it cannot be said that the surface is always clean. In addition, a problem arises, such that the contact resistance is not stable, due to the effects of natural oxidation after the film formation of the lower electrodes and variable resistors, and the effects of the atmosphere on the process for film formation for the films deposited in upper layers.